1. Field of the Invention
This invention concerns a semiconductor device and a method of manufacturing the same. In particular, it relates to a method of manufacturing a memory semiconductor device having a fine connection plug, a high performance logic semiconductor device having a fine connection plug or a local wiring. It also relates to a memory/logic embedded LSI having a memory circuit and a logic circuit together.
2. Description of Related Art
In semiconductor devices now under development for higher integration density, application of a conductive layer formed by stacking a low resistance material layer and a silicon layer such as a metal silicide layer/silicon layer or a metal layer/metal nitride layer/silicon layer instead of an existent single silicon layer has been started (layer constitution expressed by A/B means that A is an upper layer and B is a lower layer). This is because the stacked conductive layer is effective for the lowering of the sheet resistance of the conductive layer itself or reduction of contact resistance between the conductive layer and the interconnection layer disposed above it.
A first application example of the stacked conductive layer is source and drain areas of MOS (Metal Oxide Semiconductor) transistors. A structure of stacking to form a silicide layer of a metal such as titanium or cobalt on the entire surface of an impurity-doped diffusion layer comprising silicon instead of a diffusion layer of a silicon mono-layer has been used for a logic semiconductor device such as in a high speed processor. Further, study has also been made on a nickel suicide layer. When the metal silicide layer is formed over the entire surface of the diffusion layer such that both the diffusion layer resistance and the contact resistance between the diffusion layer and the upper interconnection layer are reduced. There is another technique for forming a silicide layer of metal such as titanium, cobalt or nickel on polysilicon of a gate layer simultaneously with source and drain areas so as to obtain a gate layer as a stack of metal silicide layer/polysilicon layer, which also reduces the layer resistance of the gate layer.
The method for forming the metal silicide layer on the diffusion layer also includes a method for forming a suicide layer of a metal, such as titanium, only at the bottom of a through hole on the diffusion layer after etching the through hole to the diffusion layer rather than forming the metal silicide layer over the entire surface of the diffusion layer area. This intends to reduce the contact resistance between the metal interconnection layer and the metal silicide layer is formed only at the bottom of the through hole between the metal interconnection layer and the diffusion layer. Subsequently, a contact plug for burying the through hole (hereinafter simply referred to as xe2x80x9cplugxe2x80x9d) is formed. This method is generally used for various semiconductor devices besides memory semiconductor devices.
A second application example of the stacked conductive layer is a gate layer of an MOS transistor. Layers of lower resistance have been used for a polysilicon mono-layer for the gate layer, a stacked gate layer of metal silicide layer/polysilicon layer, and a stacked gate layer of metal layer/metal nitride layer/polysilicon layer. Furthermore, a study on a laminate gate comprising a metal layer/metal nitride layer excluding the polysilicon layer has also been started.
In view of the application of the stacked conductive layer as described above, there is a demand for forming a conductive layer providing satisfactory electric contact to the surface of a lower layer comprising different materials at the bottom of the through holes after etching the through holes for connecting a diffusion layer and an interconnection layer or for connecting a gate layer and an interconnection layer, or after etching the through holes further for connecting plugs to each other.
For example, it has now been required to form a conductive layer providing satisfactory electric contact both for a metal silicide layer and a metal layer at the bottom of the through holes etched on the gate layer comprising a metal silicide layer/polysilicon layer, a metal layer/metal nitride layer/polysilicon layer, and a silicon layer at the bottom of the through holes etched on the silicon layer. Further, if a metal silicide is formed over the entire surface of the diffusion layer, it is necessary to form a conductive layer providing satisfactory electrical contact both for a metal silicide layer at the bottom of the through holes etched on a metal silicide layer/silicon layer of a diffusion layer and for a metal layer at the bottom of the through holes etched on a gate layer comprising a metal layer/metal nitride layer/polysilicon layer.
For example, in an embedded LSI where a logic circuit and a DRAM (Dynamic Random Access Memory) circuit are integrated on a single semiconductor device, or in a DRAM in which a metal silicide film identical with that in a logic semiconductor device formed to a diffusion layer of a peripheral circuit area of a high speed memory, it is necessary to form a conductive layer providing satisfactory electric contact both for the diffusion layer in which a metal silicide layer is formed on the surface of a peripheral circuit areas of a logic circuit and for a plug layer at the bottom of the through holes etched to a plug layer comprising impurity-doped polysilicon in the memory array area.
To avoid hindering the miniaturization of the semiconductor device or complicating manufacturing steps, it is necessary to form a conductive layer in one single step at the bottom of each of the through holes having a lower layer surface comprising different materials as described above.
Further, it has become necessary to form a conductive layer film in one single step at the bottom of a group of through holes of different depth, through holes or openings for local interconnections of different shape and size for the etched area so as to produce smaller and more complicated high performance semiconductor devices. Particularly, the local interconnection technique is indispensable for miniaturization and higher performance of the logic semiconductor device, and the shape of the etched area of openings for local interconnection (hereinafter simply referred to as xe2x80x9clocal interconnection holexe2x80x9d) is generally formed in a rectangular shape with a long side to short side ratio of 2 or more, in a rectangular shape or in an L-shape in which a longitudinal portion has a rectangular shape. The local interconnection is formed by burying the local interconnection hole with a metal layer.
For forming a conductive layer at each of the bottoms for the group of through holes or local interconnection holes having a lower layer surface comprising different materials as described above, or for forming a conductive layer film in one single step to each bottom of the through holes of different depths and to each bottom of the through holes or local interconnection holes having different shapes and sizes of etched area, a manufacturing method of forming a metal film is used. The method includes sputtering, such as titanium, reacting at least a portion of a metal layer in contact with a silicon layer or a metal silicide layer at the bottom of the through holes or local interconnection holes by heat treatment at about 700xc2x0 C. thereby additionally forming a metal silicide layer so as to reduce the contact resistance to silicon. The heat treatment is conducted just after the sputtering step or the reacting step.
The method is mainly used to provide a titanium silicide layer. The metal silicide layer is necessary for reducing the contact resistance between the silicon layer or silicon-containing metal silicide layer and an upper metal interconnection layer. Particularly, in the plug or local interconnection to silicon, when the plug or interconnection is formed, such as of titanium nitride, since the contact resistance increases if a reaction barrier layer comprising titanium nitride and silicon are brought into direct contact, the metal silicide layer is indispensable.
Further, also in the formation of plugs or local interconnections to a diffusion layer in which a metal silicide layer is formed over entire surface, since the silicon layer may break through the metal silicide layer by excess dry etching upon etching treatment of through holes or local interconnection holes so as to intrude into the through holes or local interconnection holes in which the silicon layer is exposed at the lower portion, it is often necessary to additionally form a metal silicide layer at the bottom of the through holes or local interconnection holes after etching. The Japanese Patent Application No. 112157/1994 discloses a manufacturing method for forming a metal silicide layer by sputtering a metal film of titanium or the like after etching a through hole, reacting a metal film in contact with a silicon layer or a metal silicide layer at the bottom of the through hole with the silicon layer or silicon in the metal silicide layer by heat treatment so as to form a metal silicide layer.
However, it has been found that a layer having a high contact resistance or a diffusion layer causing large leakage current are contained at the bottom of the through holes or local interconnection holes formed by the prior art as described above.
The problem described above becomes most significant when a second heat treatment is subsequently applied in addition to the required minimum heat treatment for forming the metal silicide layer. Particularly, if the metal silicide layer is formed over the entire surface of the diffusion layer, the surface of the diffusion layer or the junction portion of the diffusion layer formed as the metal silicide layer has low heat resistance thereby the second heat treatment often increases the contact resistance between the plug and the surface of the diffusion layer and the leakage current in the diffusion layer.
The insufficiency of the heat resistance depends on the thickness of the metal film formed by sputtering and also depends on the material of the lower layer exposed at the bottom of the contact hole. The lack of heat resistance at the surface of the junction portion of the diffusion layer formed by the prior art causes a significant problem, especially it heat treatment is required at a high temperature of 600xc2x0 C. or higher in the capacitor forming step of a semiconductor device. In other words, the heat treatment step applied in the course of forming capacitors increases the contact resistance between the plug and the surface of the diffusion layer remarkably or increases the junction leakage current of diffusion layer so as to damage the junction.
The material for the capacitive dielectric film of the capacitors in the memory circuit includes tantalum oxide or BST (barium strontium titanate) which are new in comparison with the traditionally used silicon oxynitride film. Anyway, film deposition or heat treatment at a temperature of 600xc2x0 C. or higher is necessary to obtain a capacitor with a small leakage current.
Further, film formation or heat treatment at a temperature of 600xc2x0 C. or higher is also required for manufacturing a memory circuit with a ferroelectric film, such as PZT (lead zirconium titanate) film or a SBT (strontium bismuth tantalate) film.
In the prior art, it was extremely difficult to adopt the heat treatment together with the formation of the metal silicide layer at the bottom of the through holes or on the surface of the diffusion layer for reducing the layer resistance or contact resistance. The heat treatment for forming capacitors is required to increase the etched area of the through hole so as to offset the resulted increase of contact resistance per unit area, which causes a trouble for miniaturization. Further, by lowering the heat treatment temperature in the capacitor step to prevent the increase in the contact resistance or the increase in the junction leakage current of the diffusion layer, it is necessary to increase the thickness of the capacitor dielectric film so as to suppress increase in the leakage current caused by the lowed temperature of the heat treatment. However, this increases the capacitor area, which causes a trouble in miniaturization. In anyway, the problem described above gives a significant trouble in view of the manufacture of a new high performance semiconductor device.
Also in a case of requiring to form a conductive layer in one single step at each of the bottoms of a group of through holes of different depths or through holes or local interconnection holes of different shapes and sizes for the etched area, the layer at the bottom of the through holes or local interconnection holes formed by the prior art method often results in a case where a layer exhibiting high contact resistance with respect to the plug or the local interconnection or a case where the layer in which the leakage current through the connected diffusion layer increases. In this case, it often results in a problem even in a case where heat treatment at high temperature is not applied, especially after forming the layer on the bottom.
Further, along with the demand for miniaturization, a further lower contact resistance by unit area and smaller junction leakage current are demanded even for any shallow junction, which make the prior art even less satisfactory.
The investigation by the inventors reveals that high contact resistance of the bottom layer, a large leakage current of the connected diffusion layer and, further, lack of heat resistance for the bottom layer or the diffusion layer in the prior art are attributable to the formation of a metal silicide layer with a thickness larger than an appropriate range on a layer exposed to the bottom of the through holes or the local interconnection holes, the formation of a metal mixture layer or an alloy layer having a thickness larger than an appropriate range, or the formation of a metal silicide layer with a thickness outside of the appropriate range. Particularly, it has been found that when a high heat treatment is applied after forming the bottom layer of the through hole or the local interconnection, the appropriate thickness range is narrowed.
Generally, when the thickness of the formed metal silicide layer is larger than the appropriate thickness range, the leakage current in the connected diffusion layer increases. Particularly, the junction suffers from damages through the subsequent processing step, which further increases the junction leakage current. If the thickness of the formed metal mixture layer or alloy layer is larger than the appropriate thickness range, the contact resistance increases. By the additional heat treatment, the thickness of the metal mixture layer or alloy layer increases so as to further increase the contact resistance. Then the thickness of the metal silicide layer falls below the appropriate thickness range, the contact resistance increases because (1) that the film quality of the metal silicide layer is deteriorated if it is excessively thin, and (2) that the thin metal silicide layer agglomerates by the heat treatment to cause local uneven distribution of the film thickness.
If the bottom of the through hole or the local interconnection hole is exposed when a metal layer is formed at the bottom by sputtering, forming an identical thickness metal film does not depend on the material exposed on the bottom of the through hole so long as the size of the through hole is identical. That is, a metal film of an identical thickness is formed at the bottom of a through hole where silicon is exposed, at the bottom of a through hole where a metal is exposed, and at the bottom of the through hole where a metal silicide is exposed.
The shape of coverage formed with the conventional metal film by sputtering is thicker at the central portion and thinner at the periphery on the bottom of the hole but the thickness is-identical in holes made in the same process. When heat treatment is applied subsequently, any metal formed by sputtering is reacted with silicon to form a metal silicide layer at the bottom of the hole where silicon is exposed. Also, at the bottom of the hole where the metal silicide is exposed, any metal formed by sputtering is reacted into a metal silicide layer. At the bottom of the through hole where a metal is exposed, reaction is taken place between the metal and a metal formed further by sputtering to form a metal mixture layer or an alloy layer.
When the thickness of the metal silicide layer formed by reaction with silicon at the bottom of the hole where silicon is exposed is intended to be at an appropriate thickness, the thickness of the metal silicide layer formed at the bottom of the hole where the metal silicide is exposed is often larger than the appropriate thickness. Similarly, at the bottom of the hole where the metal is exposed, a metal mixture layer or alloy layer of an excessive thickness is formed.
When it is intended to form the metal silicide layer formed at the bottom of the hole at an appropriate thickness, the thickness of the metal silicide layer formed at the bottom of the hole where silicon is exposed is often less than the appropriate thickness. Further, at the bottom of the hole where a metal is exposed, a metal mixture layer or alloy layer of a somewhat excessive thickness is formed.
When it is intended to form the metal mixture layer or alloy layer formed at the bottom of the hole where the metal is exposed at an appropriate thickness, the thickness of the metal silicide layer formed at the bottom of the hole where silicon is exposed is often less than appropriate thickness. Further, at the bottom of the hole where the metal silicide is exposed, a metal silicide layer of a somewhat insufficient thickness is formed.
In order not to damage the shallower junction required by miniaturizing a semiconductor device, the upper limit for the thickness of the metal silicide layer in contact with the diffusion layer becomes smaller. Accordingly, the range for the appropriate thickness of the metal silicide layer also becomes smaller, and it is extremely difficult to form a metal silicide layer within an appropriate range of the thickness by the prior art.
It may be theoretically considered to form metal films to the bottoms of the respective through holes by separate steps and forming a metal silicide layer of an appropriate thickness to each of the holes. However, since the layer has to be formed separately, this remarkably increases the number of steps and complicate is the steps. Therefore, it is almost impossible to apply this approach for actual manufacturing. Further, this method requires bigger alignment margins between the layers at the bottom of the through hole or the local interconnection hole, it becomes impractical, particularly, for micro semiconductor devices.
Particularly, in a case of forming a conductive layer at the bottom of local interconnection holes of different shape or different size of etched area by one single step, since the coverage by sputtering greatly depends on the aspect ratio of the local interconnection hole (depth to diameter ratio), the layer at the bottom of the local interconnection hole formed by the prior art by sputtering often contains high resistance or causes a larger junction leakage current from the connected diffusion layer to the well or the substrate.
It is impossible to classify the local interconnection holes into several groups according to size and shape so as to form metal films to the local interconnection holes of the respective groups separately by sputtering and to form a metal silicide layer of an optimal thickness for each of the holes.
As has been described-above in the etching process, in a dielectric film, at least two groups of through holes or local interconnection holes, among a first group of through holes or local interconnection holes in which a layer having a surface comprising silicon as a major constituent element is exposed at the bottom, a second group of through holes or local interconnection holes in which a layer having a surface comprising a first metal silicide as a major constituent element is exposed at the bottom, and a third group of through holes or local interconnection holes in which a layer having a surface comprising a first metal as a major constituent element is exposed at the bottom, it was impossible by the prior art method to form a layer with a low contact resistance and a small junction leakage current from a diffusion layer and having a high heat resistance at the bottom for all of the holes simultaneously.
This invention solves the foregoing problems in the prior art so as to provide a manufacturing method of a semiconductor device with low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections. This also provides a semiconductor device of higher integration density and higher performance. The manufacturing method maintains a sufficiently small junction leakage current from the diffusion layer and low contact resistance via a heat treatment step at high temperature after forming the diffusion layer and plugs to be connected therewith, thereby providing a highly integrated memory semiconductor device or a high performance memory/logic embedded LSI with micro-sized plugs.
Additionally, this invention provides a manufacturing method of a semiconductor device with a sufficiently small leakage current from the diffusion layer and low contact resistance even if its through holes having different depth, or the through holes or local interconnection holes having different shape and size of etched areas. This provides a high performance logic semiconductor device or a high performance memory/logic embedded LSI having fine plugs or local interconnections.
A manufacturing method of a semiconductor device according to this invention for attaining the principal object includes a step of forming a layer comprising a second metal silicide as a major constituent element on a layer having a surface comprising silicon or a first metal silicide as a major constituent element, and a layer comprising a second metal as a major constituent element on a layer having a surface comprising a first metal as a major constituent element, simultaneously, by one single chemical vapor deposition process to the bottom of each of openings of at least two out of three of openings groups. In the first group of through holes or local interconnection holes, a layer having a surface comprising silicon as a major constituent element is disposed at the bottom (xe2x80x9cthrough holes or local interconnection holesxe2x80x9d are hereinafter collectively referred to as xe2x80x9copeningsxe2x80x9d). In the second group of openings, a layer having a surface comprising a first metal silicide as a major constituent element is disposed at the bottom. In the third group of openings, a layer having a surface comprising a first metal as a major constituent element is disposed at the bottom etched in a dielectric film on a substrate.
A manufacturing method of a semiconductor device according to this invention for attaining the additional object comprises including a step of simultaneously forming, by one single chemical vapor deposition process, a layer comprising a second metal silicide as a major constituent element on a layer having a surface mainly comprising silicon or first metal silicide as a major constituent element, and a layer having a second metal as a major constituent element on a layer having a surface comprising a first metal as a major constituent element, to the bottom of each of a group of through holes having an etched area on the surface of the dielectric film shaped substantially circular or square, i.e., substantially symmetrical with respect to the central point of the etched area, and each bottom for each of openings having an etched area in the surface of the dielectric film shaped rectangular with a pair of long sides twice or more longer than a pair of short sides.
Another manufacturing method of a semiconductor device for attaining the additional object of the invention includes a step of simultaneously forming, by one single chemical vapor deposition process, a layer comprising a second metal silicide as a major constituent element on a layer having a surface comprising silicon or a first metal silicide as a major constituent element to the bottom of each of the first group of through holes, where a layer having a surface comprising silicon or first metal silicide as a major constituent element is disposed at a bottom, and to the bottom of each of the second group of through holes, where a layer having a surface comprising silicon or a first metal silicide as a major constituent element is disposed to the bottom. Each of the second group of through holes has a depth by twice or more deeper than each of the first group of through holes.
The manufacturing method of a semiconductor device according to this invention will be explained more specifically. For example, the plasma CVD process is practiced by using plasmas of a gas mixture comprising titanium tetrachloride and hydrogen such that a titanium silicide layer is formed on silicon when the temperature of the substrate is sufficiently high.
This is because the reaction between titanium and silicon proceeds on silicon and a reaction layer forms a silicide layer simultaneously with the formation of titanium layer by the plasma CVD process. See Technical Digest, IEDM (December, 1996), pages 361-364. It is described that the reaction between titanium and silicon proceeds on silicon at a substrate temperature of 570xc2x0 C. or higher. Further, it has also been described that the rate of forming the titanium silicide layer on silicon increases along with the increase of the substrate temperature, while the rate of forming the titanium layer on silicon dioxide is substantially saturated and constant.
A method for forming a metal silicide layer of titanium simultaneously on polycrystal silicon of the source, the drain, and the gate layer of an MOS transistor is described in U.S. Pat. No. 5,703,972.
Although not described in the cited patent, it is known that it is also possible not to form the titanium layer substantially on silicon dioxide by selecting the conditions of the chemical vapor deposition process.
On the other hand, based upon the experiment by the present inventors, when the same processing (one single plasma CVD process) is applied on metal, such as tungsten, simultaneously, on silicon, the titanium layer, even if formed on the metal, such as tungsten, remains as a titanium layer since reactant silicon is not present. This may be anticipated from the result on silicon dioxide described above but it is demonstrated also by the experiment.
It has been found from the experiment described above that the rate of forming the titanium layer on the metal is substantially constant within a temperature range while the titanium silicide layer is formed in the same manner on silicon dioxide. Further, it has also been found that the formation rate is identical for the dielectric film other than silicon dioxide (ex, silicon nitride).
Furthermore, a metal silicide layer of thin thickness is formed on the metal silicide layer compared with that on silicon when one single film deposition processing is applied on the silicide layer of metal, such as titanium, simultaneously with that on silicon. This is because the reaction between titanium and silicon proceeds on silicide simultaneously with the formation of the titanium layer in the same manner as that for the formation of the titanium silicide layer on silicon when the metal is titanium so as to form a titanium silicide layer, but the thickness of the resulted titanium silicide layer is reduced since the amount of silicon near the surface is smaller than that on the silicon.
In the experiment described above, a plasma CVD process by titanium tetrachloride and hydrogen was used, but the kind and the thickness of the film to be formed generally differ depending on the material on the substrate surface. This is also true in forming the silicide layer by utilizing the reaction with silicon on the substrate surface.
Further, similar effects are obtained by a plasma CVD process using halides of metal (such as tantalum, tungsten or molybdenum), cobalt compounds having carbonyl groups (dicobalt octacarbonyl Co2(CO)8, a cobalt tricarbonyl nitrosyl (Co(CO)3NO, etc.) or an organic material containing the metals described above as one of starting materials. This was also applicable in a chemical vacuum deposition process using titanium tetrachloride or the like as a starting material.
In each of the chemical vapor deposition processes described above, the coverage shape does not depend on the depth, shape or size of the etched area as in a sputtering process for forming the conductive film in one single step the inside of opening of different shape or the size of the etched area.
The invention is different from the prior art that at least two out of three groups openings are present on the substrate. In the first group of openings, a layer comprising silicon as a major constituent element is exposed at the bottom. In the second group of openings, a layer comprising a metal silicide as a major constituent element is exposed at the bottom. In the third group of openings, a layer comprising a metal as a major constituent element is exposed at the bottom. While one single chemical vapor deposition process is applied simultaneously on the three groups of the openings, and layers of different materials or different thickness are formed onto the bottom of the respective openings.
In a case of forming a conductive layer by one single step inside each of the through holes of different depths or sizes, and each of the openings different in the shape or the size of an etched area. The coverage shape does not depend on the depth, the shape or the size the etched area as in a sputtering process.
As has been described above, through holes of low contact resistance and with small junction leakage current for the connected diffusion layer can be formed simultaneously by one single CVD process. Further, even after heat treatment at a high temperature for forming the diffusion layer and the through holes, it still has a small leakage current from the diffusion layer and low contact resistance in a memory semiconductor device having micro-sized through holes, a capacitor device, or a high performance semiconductor device embedded with a memory circuit and a logic circuit.
While this invention is most effective for manufacturing a memory semiconductor device or memory logic embedded LSI, it is also applicable to manufacture other semiconductor devices, such as logic semiconductor devices.
Other and further objects, features and advantages of the invention will appear more fully from the following description.